1. Field of the Invention
This invention relates generally to voltage boost circuits, and, more particularly, to circuits which provide a boosted voltage without overstressing any of the circuit's active devices.
2. Description of the Related Art
An integrated circuit (IC) may require voltages having values that are higher and/or lower than the available supply voltages. This may include a voltage value which is above the positive power supply voltage, and a voltage below the lowest available negative power supply voltage (or ground).
Conventionally, signals exceeding an IC's supply voltages have been generated with complementary PMOS and NMOS devices. One such example is shown in U.S. Pat. No. 6,828,850 to LeChevalier. Here, a voltage multiplier block (106) increases the available supply voltage, which powers a level shifter (108) which includes an NMOS FET (216A). In operation, the drain of the level shifter FET is toggled between ground and the increased supply voltage. The FET must be specially designed to withstand the larger supply voltage across its drain to source; otherwise, the increased voltage may exceed the devices' maximum allowable voltage ratings, thereby overstressing the MOSFETs and possibly degrading their long term reliability.